Inbound posted write requests and messages must be allowed to progress past stalled inbound non-posted requests. Outbound non-posted read and non-posted write completions must be allowed to progress past stalled inbound non-posted requests. However, the rules below apply to inbound transactions received on the same interface. In general, there are no ordering requirements between transactions received on different PCI Express interfaces. I'm loking at a server board, as I've developed an app that could really use 58 lanes of PCIe, and so have been trying to 'digest' the 5520 IOH docs here's a piece on message ordering from Intel: Ya gotta cut the 'driver and BIOS guys' some slack they'll get it all ironed out eventually It seemed like they only ever released one 'second gen' board (the X58-UD3R 1.6/1.7) with the early hardware kinks ironed out, and then it's off to the races again with the 'A' suffix boards, and not one, but two untried technologies - SATA3 and USB3! Eeek! The 'hexacores' are due for release, and I'm thinking 'server board' (wish GB made some - better the devil you know than the devil you don't!)

I predicted, and avoided, the early debacles with the 1366/1156 stuff, but have been drooling over the hardware for a while, now. There's always a certain amount of 'suffering' that goes with the advent of new technologies - and I always try to sidestep it for, like, the first year but, lately, it never stops. I'm curious myself - are they 'WHQL'd yet? I have tried to get 'spec level' info on Marvell's chip - and they don't appear to make it available they appear to only have mechanisms in place to deal with wholesale customers. Seriously - my second guess - 'early adopter's blues'! I know that RAID drivers were not yet available when the new boards were released - and are, now. You mean you haven't seen the little 'flip tab' that lets you pop the 9128 out and use it in your laptop?

Marvell 91xx config device driver